SI4022-A0-FT【PDF 14/20 页】IC TX FSK UNI 868/915MHZ 16TSSOP

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Sheet目录57

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Si4022

bw1 bw0

PLL bandwidth

15 kHz

30 kHz

60 kHz

120 kHz

bit 15 14 13 12 11 10

POR

0 exlp ctls 0 dcal bw1 bw0 dsfi ewi

B0CAh

FFIT

The number of data bits in the FIFO has gone below the preprogrammed limit

FFEM

FIFO is empty

FFOV

FIFO overflow

LBD

Low battery detect, the power supply voltage is below the preprogrammed limit

WK-UP

Wake-up timer overflow

POR

Power-on reset

bit 15 14 13 12 11 10

POR

Status Register Read Command

With this command, it is possible to read the status register of the chip through the SDO pin.

Status Register Read Sequence

Extended Features Command:

Bit 7 <exlp>:

Enables low power mode for the crystal oscillator.

Bit 6 <ctls>:

Clock tail selection bit. Setting this bit selects 512 cycle long clock tail instead of the default 128.

Bit 4 <dcal>:

Disables the wake-up timer autocalibration.

Bit 3-2 <bw1:bw0>: Select the bandwidth of the PLL.

Bit 1 <dsfi>:

Disables autosleep on FIFO interrupt if set to 1.

Bit 0 <ewi>:

Enables the automatic wake-up on any interrupt event.

nSEL

SCK

SDI

SDO

status out

FFIT

FFEM

FFOV

LBD

WK-UP

POR

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